Platform-based design is becoming a preferred methodology for integrated circuit implementation as the semiconductor industry attempts to keep pace with increasing circuit complexity. The basic idea behind platform-based design is to avoid the need to design a semiconductor chip from scratch. A library of generic blocks or components is defined and designed for easy implementation and reuse as a sub-component of a complete chip design.
There are several approaches to platform-based integrated circuit design. One approach is the “standard cell” approach. A standard cell comprises a plurality of circuitry components such as resistors, transistors, etc., and has a predefined and uniform geometry and pin layout. Standard cells, in turn, are organized into blocks that carry out particular functions, such as registers or processing. Hence, an engineer may choose a standard cell from a catalog or library of such cells to carry out some desired function. A standard cell has a standardized pin layout and configuration that makes it easily interconnectable with other such cells. While standard cells are typically easier and faster for a designer to lay out and interconnect, they may not be optimized for performance. A “hard macro” (or simply “macro”) approach, by contrast, utilizes a circuitry layout that is customized for the particular function that is being carried out. Macros, while optimized for performance and organized into and treated like other blocks, typically have irregular and unpredictable geometry and signal/power pin locations.
Another emerging trend in the semiconductor industry is the system-on-a-chip (“SOC”) design methodology which has, as its name implies, the goal of placing many integrated circuits onto a single semiconductor chip to form a fully contained system. Among the many design challenges facing the SOC integrator is the physical placement and routing of the design, a process referred to as “floorplanning”. While floorplanning would be easiest if the designer could choose exclusively from a library of standard cells, in reality, it is almost always necessary to use a mix of standard cells and macros. One particularly troublesome aspect of floorplanning is power routing. Because macros contain signal and power pins in irregular locations, while standard cells possess much more regularity, the routing of power among macros and standard cells is often cumbersome and inefficient. Inefficient integration of circuit blocks such as standard cells and macros can make the chip prohibitively large and cause unwanted timing and delay side effects.
One common power routing technique involves routing power busses and signals using channels formed around and between each standard cell or macro. This approach, however, wastes precious die space that could be used for other purposes or even eliminated. Moreover, because channel routing precludes further cell placement in or near the channel, the area devoted to the channel (often between 10 μm and 50 μm wide) creates a low density, underutilized region for the active and polycrystalline lower layers. This technique also typically involves use of an additional power bus between the I/O ring and chip core, a practice that is likewise wasteful and can create uneven power distribution for the chip.